1. Technical Field
The disclosure relates to a semiconductor manufacturing method thereof. More particularly, the disclosure relates to a packaging structure manufacturing method.
2. Technical Art
The technology of stacking chips can shorten the transmission pathway of electronic signals and provide an efficient technique to integrate different material chips. In terms of the latter, it can stack up the high-frequency power amplifier chips and radio frequency chips, or can be integrated with the micro-electro mechanical system devices. Moreover, the overall performance of the stacked-chip packaging structure can be improved if the passive elements can be integrated effectively. Therefore, it is essential to provide a high quality and highly integrated interposer structure with passive elements between the stacked chips.
Referring to FIG. 1, it is a schematic view of a conventional stacked circuit device. The conventional stacked circuit device 100 is disclosed in U.S. Pat. No. 6,661,088, wherein it includes a chip 110, an interposer structure 120 and a substrate 130. A plurality of pads 112 disposed on the chip 110 is electrically connected to the corresponding multiple pads 132 disposed on the substrate 130 through the interposer structure 120. The main purpose of the interposer structure 120 is to serve as circuit redistribution.
Another conventional stacked circuit device is provided for the purpose of integrating different type circuit elements such as active elements and passive elements to the interposer structure. Referring to FIG. 2, it is a schematic view of another conventional stacked circuit device. The conventional stacked circuit device 200 disclosed in U.S. Pat. No. 6,614,106 includes a chip 210, an interposer structure 220 and a base substrate 230. It should be noted that for the sake of clarified description, FIG. 2 also shows the enlarged view of the interposer structure 220. A plurality of terminals 212 of the chip 210 are electrically connected to the corresponding multiple terminals 222 of the interposer structure 220. Whereas the other terminals 224 of the interposer structure 220 are electrically connected to the set of terminals of the base substrate 230. The interposer structure 220 comprises an insulating film 226, a semiconductor substrate 228, and a plurality of circuit elements 229 such as the active and passive elements which are disposed in the insulating film 222.
Other related techniques of fabricating passive elements on the semiconductor base material of the interposer structure are disclosed in U.S. Pat. Nos. 6,500,724, 6,819,001 and 6,274,937. However, fabricating passive elements on the semiconductor base material may leads to low quality factor of inductive elements, inferior capacitance due to the limitations of material and processing temperature of semiconductor, and poor resistance of the resistive elements.
To overcome the aforementioned drawbacks, the method of fabricating passive elements on the insulating materials, ceramic or plastic, of the interposer structure are proposed and the related techniques are described in the U.S. Pat. Nos. 6,933,601, 6,611,419 and 5,530,288. However, it often cost much since to fabricate inductive elements on ceramic base substrate, the high priced material, silver, is often used. On the other hand, the quality factor of the inductive elements is decreased while adopting epoxy resin as the dielectric material to fabricate the inductive element on a plastic substrate. In addition, it may cause poor capacitance when fabricating capacitive elements on the insulating substrate, less process compatibility when manufacturing resistive elements on the ceramic substrate, and unstable resistance when forming the resistive elements on the plastic substrate. Also, it may make the final product of the interposer structure big and thick when fabricating passive elements on the insulating base materials.